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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
June. 2000. Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
S6A0069 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1, 2-line with 5 x 8 or 5 x 11 dots format.
FUNCTIONS
* * * * * * * * *
Character type dot matrix LCD driver & controller. Internal driver: 16 common and 40 segment signal output. Easy interface with 4-bit or 8-bit MPU Display character pattern : 5 x 8 dots format (204 kinds), 5 x 11 dots format (32 kinds) The special character pattern can be programmable by Character Generator RAM directly. A customer character pattern can be programmable by mask option. It can drive a maximum 80 characters by using the S6A0065 or S6A2067 externally. Various instruction functions Automatic power on reset
FEATURES
*
Internal Memory - Character Generator ROM (CGROM): 10,080 bits (204 characters x 5 x 8 dot) & ( 32 characters x 5 x 11 dot) - Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot) - Display Data RAM (DDRAM): 80 x 8 bits (80 characters max.)
*
Low Power Operation - Power supply voltage range: 2.7 to 5.5V (VDD) - LCD drive voltage range: 3.0 to 13.0V (VDD - V5)
* * * * *
CMOS process Programmable duty cycle: 1/8, 1/11, 1/16 Internal oscillator with an external resistor Low power consumption Bare chip available
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40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
BLOCK DIAGRAM
VDD GND V1 V2 V3 V4 V5 Busy Flag Parallel to Serial Data Conversion Circuit 5 Character Generator ROM (CGROM) 10080 bits 8 5 Character Generator RAM (CGRAM) 512 bits 8 8 8 8 Instruction Register (IR) 8 Instruction Decoder (ID) 7 7 Display Data RAM (DDRAM) 80x8 bits
Cursor & Blink Controller
R/W RS E DB0DB3 DB4DB7 Input/ Output Buffer
8
Data Register (DR)
40-bit Shift Register
40-bit Latch Circuit
Segment Driver
40 S1-S40
D
7 7
Address Counter 16-bit Shift Register Common 16 Driver C1-C16 CLK1 CLK2 M
OSC1 OSC2
Timing Generator Circuit
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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CONFIGURATION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 GND OSC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S6A0069
Y
(0, 0)
X
Chip size: 4060 x 3840 Pad size: 100 x 100 Unit: m
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
S39 S40 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 DB7 DB6 DB5 DB4 DB3 DB2
4
OSC2 V1 V2 V3 V4 V5 CLK1 CLK2 VDD M D RS R/W E DB0 DB1
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
PAD CENTER COORDINATES
Unit: um
PAD NUM. PAD NAME COORDINATE X Y PAD NUM. PAD NAME COORDINATE X Y PAD NUM. PAD NAME COORDINATE X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 GND OSC1 OSC2 V1 V2
-1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1864 -1120 -970 -820
1465 1340 1215 1090 965 840 715 590 465 340 215 90 -35 -160 -285 -410 -535 -660 -785 -910 -1034 -1159 -1285 -1414 -1754 -1754 -1754
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
V3 V4 V5 CLK1 CLK2 VDD M D RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 C1 C2 C3 C4 C5 C6 C7 C8
-670 -520 -370 -220 -70 80 230 380 518 642 768 894 1018 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 1864
-1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1754 -1488 -1362 -1238 -1112 -988 -862 -665 -540 -415 -290 -165 -40 85 210
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
C9 C10 C11 C12 C13 C14 C15 C16 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23
1864 1864 1864 1864 1864 1864 1864 1864 1864 1864 886 760 636 510 386 260 136 10 -114 -240 -364 -490 -614 -740 -864 -989
335 460 585 710 835 960 1085 1210 1341 1466 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754 1754
5
S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PIN DESCRIPTION
PIN VDD GND V1 - V5 S1 - S40 C1 - C16 OSC1 OSC2 No 33 23 26- 30 1-22, 63- 80 47-62 24 25 O O I O I/O NAME Supply Voltage DESCRIPTION Supply Voltage for logical circuit (+3V 10%,+5V 10%) 0V (GND) Bias voltage level for LCD driving. Segment output Common output Oscillator Oscillator Extension driver Latch clock Extension driver Shift clock Alternated signal for LCD driver output Display data interface Segment signal output for LCD drive. Common signal output for LCD drive. When use internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1. extension driver latch clock. extension driver shift clock. Outputs the alternating signal to convert LCD driver waveform to AC. Outputs extension driver data (the 41th dot's data) Used as register selection input. When RS = "High", Data register is selected. When RS = "Low", Instruction register is selected. Used as read/write selection input. When R/W = "High", read operation. When R/W = "Low", write operation. Read/write enable signal. When 8-bit bus mode, used as low order bidirectional data bus. In 4-bit bus mode open these pins. I/O DB4DB7 43-46 Data bus 0-7 When 8-bit bus mode, used as high order bidirectional data bus. In case of 4bit bus mode, used as both high and low order. DB7 is used for Busy Flag output. LCD LCD External Resistor/ Oscillator OSC1 Extension driver Power Supply INTERFACE
CLK1 CLK2
31 32
O O
M
34
O
Extension driver Extension driver
D
35
O
RS
36
I
Register select
MPU
R/W E DB0DB3
37 38 39-42
I I
Read/Write Read/write enable
MPU MPU MPU
MPU
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40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
FUNCTION DESCRIPTION
System Interface This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM. The target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode. Table 1. Various Kinds of Operations according to RS and R/W Bits RS L L H H Busy Flag (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. R/W L H L H Operation Instruction Write operation (MPU writes Instruction code into IR) Read Busy Flag (DB7) and address counter (DB0 - DB6) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data from DR)
Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 - DB6 ports.
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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Display Data RAM (DDRAM) DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Figure1.)
MSB AC6 AC5 AC4 AC3 AC2 AC1
LSB AC0
Figure 1. DDRAM Address 1) 1-line Display In case of 1 line display, the address range of DDRAM is 00H - 4FH. Extension driver will be used. Fig-2 shows the example that 40 segment extension driver is added.
Display position 1 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B 13 14 15 16 0F SEG40 17 10 18 11 19 12 20 13 21 14 22 15 23 16 24 17 SEG40
COM1 COM8
00 SEG1
0C 0D 0E
S6A0069
SEG40
SEG1 Extension driver (40 SEG)
SEG1 Extension driver (40 SEG) DDRAM Address
1
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10 0A
11 0B
12
13
14
15 0F
16 10 SEG40
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18 SEG40
COM1 COM8
01 SEG1
0C 0D 0E
S6A0069
SEG40
SEG1 Extension driver (40 SEG) (After Shift Left)
SEG1 Extension driver (40 SEG)
1
2 00
3 01
4 02
5 03
6 04
7 05
8 06
9 07
10 08
11 09
12 0A
13 0B
14
15
16
17 0F
18 10
19 11
20 12
21 13
22 14
23 15
24 16 SEG40
COM1 COM8
4F SEG1
0C 0D 0E SEG40
S6A0069
SEG40
SEG1 Extension driver (40 SEG) (After Shift Right)
SEG1 Extension driver (40 SEG)
Figure 2. 1-line x 24 Character Display with 40 Segment Extension Driver
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S6A0069
2) 2-line Display In case of 2 line display, the address range of DDRAM is 00H - 27H, 40H - 67H. Extension driver will be used. Figure 3 shows the example that 40 segment extension driver is added.
Display position 1 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 12 13 14 15 16 17 10 18 11 19 12 20 13 21 14 22 15 23 16 24 17
COM1 COM8 COM9 COM16
00
0A 0B 0C 0D 0E 0F
DDRAM Address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57
SEG1
S6A0069
SEG40
SEG1 Extension driver (40 SEG) SEG40
SEG1 Extension driver (40 SEG) SEG40
1
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10
11
12
13
14
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
COM1 COM8 COM9 COM16
01
0A 0B 0C 0D 0E
41
42
43
44
45
46
47
48
49
4A 4B 4C 4D 4E
4F
50
51
52
53
54
55
56
57
58
SEG1
S6A0069
SEG40
SEG1 Extension driver (40 SEG) SEG40 (After Shift Left)
SEG1 Extension driver (40 SEG) SEG40
1
2 00
3 01
4 02
5 03
6 04
7 05
8 06
9 07
10 08
11 09
12
13
14
15
16
17 0F
18 10
19 11
20 12
21 13
22 14
23 15
24 16
COM1 COM8
27
0A 0B 0C 0D 0E
COM9 67 40 41 42 43 44 45 46 COM16
SEG1 S6A0069 SEG40
47
48
49
4A 4B 4C 4D 4E
4F
50
51
52
53
54
55
56
SEG1 Extension driver (40 SEG) SEG40 (After Shift Right)
SEG1 Extension driver (40 SEG) SEG40
Figure 3. 2-line x 24 Character Display with 40 Segment Extension Driver
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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
CGROM (Character Generator ROM) CGROM has a 5 x 8 dots 204 characters pattern and a 5 x 10 dots 32 characters pattern. CGROM has 204 character patterns of 5 x 8 dots, and 32 character patterns of 5 x 11 dots.
CGRAM (Character Generator RAM) CGRAM has up to 5 x 8 dot, 8 characters. By writing font data to CGRAM, user defined characters can be used (refer to Table 5)
Timing Generation Circuit Timing generation circuit generates clock signals for the internal operations.
LCD Driver Circuit LCD Driver circuit has 16 common and 40 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. When each common is selected by 16 bit common register, segment data also output through segment driver from 40 bit segment latch. In case of 1-line display mode, COM1- COM8 have 1/8 duty or COM1 COM11 have 1/11duty, and in 2-line mode, COM1 - COM16 have 1/16 duty ratio.
Cursor / Blink Control Circuit It controls cursor/blink ON / OFF at cursor position.
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40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
Table 5. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character Code (DDRAM data) CGRAM Address D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 1 1 1 1 . . . . . 0 0 0 0 x 1 1 1 0 0 . . . . . 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x
P6 x
CGRAM Data P5 P4 P3 P2 x 0 1 1 1 1 1 1 0 . . . . . 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0
P1 1 0 0 1 0 0 0 0
P0 0 1 1 1 1 1 1 0
Pattern number Pattern 1
. . . . .
. . . . .
. . . . .
0 0 0 0 1 1 1 1
. . . . .
. . . . .
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
x
x
x
. . . . .
0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0
1 1 1 1 1 1 1 0
. . . . . Pattern 8
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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION
Outline To overcome the speed difference between internal clock of S6A0069 and MPU clock, S6A0069 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 5 ) Instruction can be divided largely four kinds, (1) S6A0069 function set instructions ( set display methods, set data length, etc.) (2) Address set instructions to internal RAM (3) Data transfer instructions with internal RAM (4) Others. The address of internal RAM is automatically increased or decreased by 1.
NOTE: During internal operation, Busy Flag (DB7) is read High. Busy Flag check must precede the next instruction. When an MPU program with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW".
Contents 1) Clear Display
RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). 2) Return Home
RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 -
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.
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S6A0069
3) Entry Mode Set
RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 SH
Set the moving direction of cursor and display. I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM. SH: Shift of entire display When DDRAM read (CGRAM read/write) operation or SH = "Low", shift of entire display is not performed. If SH = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right). 4) Display ON / OFF Control
RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1 bit register. D : Display ON/OFF Control Bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. C : Cursor ON/OFF Control Bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B : Cursor Blink ON/OFF Control Bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. 5) Cursor or Display Shift
RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 DB0 -
Shifting of right/left cursor position or display without writing or reading of display data. This instruction is used to correct or search display data (Refer to table 6). During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line. Note that display shift is performed simultaneously in all the lines. When displayed data is shifted repeatedly, each line is shifted individually. When display shift is performed, the contents of the address counter are not changed.
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40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 6. Shift Patterns According to S/C and R/L Bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, AC is decreased by 1 Shift cursor to the right, AC is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
6) Function Set
RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 F DB1 DB0 -
DL : Interface Data Length Control Bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. N : Display Line Number Control Bit When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. F : Display Font Type Control Bit When F = "Low", it means 5 x 8 dots format display mode When F = "High", 5 x 11 dots format display mode. 7) Set CGRAM Address
RS 0 R/W DB7 0 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. 8) Set DDRAM Address
RS 0 R/W DB7 0 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". 9) Read Busy Flag & Address
RS 0 R/W DB7 1 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
This instruction shows whether S6A0069 is in internal operation or not. If the resultant BF is High, it means the internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be performed. In this instruction you can read also the value of address counter.
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S6A0069
10) Write Data to RAM
RS 1 R/W DB7 0 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction (DDRAM address set, CGRAM address set). RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. 11) Read Data from RAM
RS 1 R/W DB7 1 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly.
NOTE: In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction.
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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 7. Instruction Table Instruction Code
Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description Instruction Code
Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. Set DDRAM address to "00H" from AC and return cursor to its
Execution time (fsoc=270kHz)
1.53ms
Clear Display
0
0
0
0
0
0
0
0
0
1
Return Home
0
0
0
0
0
0
0
0
1
X
original position if shifted. The contents of DDRAM are not changed.
1.53ms
Entry Mode Set Display ON/OFF Control Cursor or Display Shift
Assign cursor moving direction 0 0 0 0 0 0 0 1 I/D SH and make shift of entire display enable. Set display(D), cursor(C), and 0 0 0 0 0 0 1 D C B blinking of cursor(B) on/off control bit. Set cursor moving and display 0 0 0 0 0 1 S/C R/L X X shift control bit, and the direction, without changing DDRAM data. Set interface data length (DL : 439s 39s 39s
Function Set
0
0
0
0
1
DL
N
F
X
X
bit/8-bit), numbers of display line (N : 1-line/2-line), display font type(F : 5 X 8 dots/ 5 X 11 dots)
39s
Set CGRAM Address Set DDRAM Address Read Busy Flag and Address Write Data to RAM Read Data from RAM
0
0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Set CGRAM address in address counter. Set DDRAM address in address counter. Whether during internal operation
39s
0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
39s
0
1
BF
AC6
AC5
AC4
AC3
AC2
AC1
AC0
or not can be known by reading BF. The contents of address counter can also be read.
0s
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM).
43s
1
1
D7
D6
D5
D4
D3
D2
D1
D0
43s
NOTE: When an MPU program with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc is necessary for executing the next instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW".
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40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
INTERFACE WITH MPU 1) Interface with 8-bit MPU When interfacing data length is 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7. Example of timing sequence is shown below.
RS R/W
E Internal signal DB7 DATA
Internal Operation No Busy
Busy
Busy
DATA
Instruction
Busy Flag Check
Busy Flag Check
Busy Flag Check
Instruction
Figure 4. Example of 8-bit Bus Mode Timing Diagram
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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
2) Interface with 4-bit MPU When interfacing data length is 4-bit, only 4 ports, from DB4 to DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by two times. Busy Flag outputs "High" after the second transfer are ended. Example of timing sequence is shown below.
RS R/W
E Internal signal DB7 D7 D3 Busy
Internal Operation No Busy
AC3
AC3
D7
D3
Instruction
Busy Flag Check
Busy Flag Check
Instruction
Figure 5. Example of 4-bit Bus Mode Timing Diagram
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40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
APPLICATION INFORMATION ACCORDING TO LCD PANEL 1) LCD Panel: 8 Character x 1-line Character Format; 5 x 7 dots + 1-cursor line (1/4 Bias, 1/8 Duty)
C1 . . . C7 C8 S1 S6A0069 . . .
S10 S38 S39 S40 ..
2) LCD Panel: 8 Character x 1-line Character Format; 5 x 10 dots + 1 cursor line (1/4 Bias, 1/11 Duty)
C1
. . . C10 C11 S6A0069 S1 . . .
S10 S38 S39 S40 ..
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S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
3) LCD Panel: 8 Character x 2-line Character Format; 5 x 7 dots + 1-cursor line (1/5 Bias, 1/16 Duty)
C1 . . . C7 C8 C9 . . . S6A0069 C15 C16 S1 . . .
S10 S38 S39 S40 ..
20
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
4) LCD Panel: 16 Character x1-line Character Format; 5x7 dots + 1-cursor line (1/5 Bias, 1/16 Duty)
C1 . . . C7 C8 S1 . . .
S6A0069
S10 S39 S40 C9 . . . C16 ..
21
S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
5) LCD Panel: 4 Character x 2-line Character Format; 5 x 7 dots + 1-cursor line (1/4 Bias, 1/8 Duty)
S1 . . .
S10 S18 S19 S20 .. C1 . . . C7 C8 S6A0069 S21 . . . S30 S38 S39 S40 ..
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40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
6) APPLICATION CIRCUIT
LCD Panel C1-C16 S1-S40 D OSC1 OSC2 S6A0069 VSS M CLK1 CLK2 VDD V1 V2 V3 V4 V5 DB0-DB7 To MPU SC1-S4C0 DL2 DL1 DL1 DR2 FCS SHL1 CL1 CL2 SHL2 VSS M VDD V6 V5 V4 V3 S6A0065 V2 V1 VEE SC1-S4C0 DL2 DL1 DL1 DR2 FCS CL1 SHL1 CL2 SHL2 M VSS VDD S6A0065 V6 V5 V4 V3 V2 V1 VEE SC1-S4C0 DL2 DL1 DL1 DR2 FCS CL1 SHL1 CL2 SHL2 M VSS VDD V6 V5 V4 V3 V2 V1 VEE S6A0065
VDD V1 V2 V3 V4 V5 VLCD (1/5 bias)
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GND or Other voltage
NOTE: When S6A0065 is externally connected to the S6A0069, you can increase the number of display digits up to 80 characteristics.
S6A0069
40 SEG / 16 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
BIAS VOLTAGE DIVIDE CIRCUIT 1) 1/4 bias, 1/8 or 1/11 duty 2) 1/5 bias, 1/16 duty
VDD
R R R
VDD V1 V2 V3 V4 V5 S6A0069
VDD
R R R R
VDD V1 V2 V3 V4 V5
S6A0069
R GND or Other voltage
R GND or Other voltage
24
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
INITIALIZING When the power is turned on, S6A0069 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. (1) Display Clear instruction: Write "20H" to all DDRAM (2) Set Functions instruction DL = 1 : 8-bit bus mode N = 1 : 2-line display mode F = 0 : 5 X 8 font type (3) Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF (4) Set Entry Mode instruction I/D = 1 : Increment by 1 SH = 0 : No entire display shift FRAME FREQUENCY Programmable Driving Method by the same font mask option: Display waveform A-Type, B-Type 1) 1/8 Duty Cycle A) A-Type Waveform
1-line selection period 1 VDD V1 COM1 ... ... V4 V5 ...
V1 ... V4 V5 1 Frame 1 Frame COM1
2
3
4
...
7
8
1
2
3
...
7
8
B) B-Type Waveform
VDD
Line selection period One Frame Frame frequency
= 400 clocks = 400 x 8 x 3.7s = 11850 s = 11.9 ms (1 clock = 3.7 s, fosc = 270kHz) = 1 / 11.9ms = 84.3Hz
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S6A0069
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
2) 1/11 duty cycle A) A-type Waveform
1-line selection period 1 VDD V1 COM1 ... ... V4 V5 ...
V1 ... V4 V5 1 Frame 1 Frame COM1
2
3
4
...
10
11
1
2
3
...
10
11
B) B-type Waveform
VDD
Line selection period One Frame Frame frequency
= 400 clocks = 400 x 11 x 3.7s = 16300s = 16.3ms (1 clock = 3.7s , fosc = 270kHz) = 1 / 16.3 ms = 61.4 Hz
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16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
3) 1/16 duty cycle A) A-type Waveform
1-line selection period 1 VDD V1 COM1 ... ... V4 V5 ...
V1 ... V4 V5 1 Frame 1 Frame COM1
2
3
4
...
15
16
1
2
3
...
15
16
B) B-type Waveform
VDD
Line selection period One Frame Frame frequency
= 200 clocks = 200 x 16 x 3.7s = 11850 s = 11.9 ms (1 clock = 3.7s, fosc = 270kHz) = 1 / 11.9ms = 84.3Hz
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S6A0069
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INITIALIZING BY INSTRUCTION
1) 8-bit Interface Mode (Condition: fosc = 270kHz)
Power On
Wait for more than 30ms after DD rises to 4.5 V. V Wait for more than 40ms after DD rises to 2.7 V. V 0 N Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 N DB2 F DB1 X DB0 0 X F 1 Wait for more than 39 s D 1 Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 C B 1 0 B 1 Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 Blink ON Cursor ON Blink OFF 0 Cursor OFF Display ON Display ON Display OFF 1 2-line mode 1-line mode
0
Display OFF
Wait for more than 39 s
Wait for more than 1.53ms s 0 I/D Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 0 SH SH 1 Initialization End Entire shift on Entire shift off 1 Increment mode Decrement mode
28
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
2) 4-bit Interface Mode (Condition: fosc = 270kHz)
Power On 0 D/L Wait for more than 30ms after DD rises to 4.5 V. V Wait for more than 40ms after DD rises to 2.7 V. V N Function Set RS 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 N 0 0 F 1 1 X DL 0 X X X X X X X X X X X X X F 1 Display on Display off 1 2-line mode 1 8-bit mode 4-bit mode
0
1-line mode
Wait for more than 39 s
0 D 1
Display off Display on Cursor off Cursor on Blink off Blink on
Display ON/OFF Control 0 RS 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 D 0 C 0 B X X X X X X X X B 1 Wait for more than 39 s 0 C 1
Display Clear RS 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 X X X X X X X X
Wait for more than 1.53 s m 0 Entry Mode Set RS 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 I/D 0 SH X X X X X X X SH X 1 Entire shift on 0 Entire shift off I/D 1 Increment mode Decrement mode
Initialization End
29
S6A0069
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
MAXIMUM ABSOLUTE LIMIT
Maximum Absolute Power Ratings Characteristic Power Supply Voltage LCD Drive Voltage Input Voltage Symbol VDD VLCD VIN Unit V V V Value -0.3 to +7.0 VDD-15.0 to VDD+0.3 -0.3 to VDD+ 0.3
.Voltage greater than above may damage the circuit (VDD V1 V2 V3 V4 V5)
Temperature Characteristics Characteristic Operating Temperature Storage Temperature Symbol TOPR TSTG Unit C C Value -30 to +85 -55 to +125
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16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 4.5V to 5.5V, Ta = -30 to +85C) Characteristic Operating Voltage Operating Current Input Voltage (1) (except OSC1) Input Voltage (2) (OSC1) Output Voltage (1) (DB0 to DB7) Output Voltage (2) (except DB0 to DB7) Voltage Drop Input Leakage Current Input Low Current Internal Clock (external Rf) Symbol VDD IDD VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG ILKG IIL f OSC1 f OSC External Clock duty t R, t F LCD Driving Voltage VLCD VDD-V5 (1/5, 1/4 bias) Condition Internal oscillation or external clock (VDD = 5.0V, fosc = 270kHz) IOH = -0.205mA IOL = 1.2mA IO = -40A IO = 40A IO = 0.1mA VIN = 0V to VDD VIN = 0V, VDD = 5V (pull up) Rf = 91k 2% (VDD = 5V) Min 4.5 2.2 -0.3 VDD-1.0 -0.2 2.4 0.9VDD -1 -50 190 125 45 3.0 Typ 0.35 -125 270 270 50 Max 5.5 0.6 VDD 0.6 VDD 1.0 V 0.4 0.1VDD 1 V 1 1 -250 350 350 55 0.2 13.0 A V V Unit V mA
V
kHz kHz % A V
31
S6A0069
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
DC Characteristics (VDD = 2.7V to 4.5V, Ta = -30 to +85C) Characteristic Operating Voltage Operating Current Input Voltage (1) (except OSC1) Input Voltage (2) (OSC1) Output Voltage (1) (DB0 to DB7) Output Voltage (2) (except DB0 to DB7) Voltage Drop Input Leakage Current Input Low Current Internal Clock (external Rf) Symbol VDD IDD VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG ILKG IIL f OSC1 f OSC2 External Clock duty t R, t F LCD Driving Voltage
NOTE: LCD Driving Voltage
Condition Internal oscillation or external clock (VDD = 3.0V, fosc = 270kHz) IOH = -0.1mA IOL = 0.1mA IO = -40A IO = 40A IO = 0.1mA VIN = 0V VDD VIN = 0V, VDD = 3V (pull up) Rf = 75k 2% (VDD = 3V)
Min 2.7 0.7 VDD -0.3 0.7VDD 0.75 VDD 0.8VDD -1 -10 190 125
Typ 0.15 -50 270 270 50 -
Max 4.5 0.3 VDD 0.55 VDD 0.2 VDD 0.2 VDD 0.2VDD 1
Unit V mA
V
V
V
V
V 1 1 -120 350 410 55 0.2 13.0 A
kHz kHz % S V
-
45 -
VLCD
VDD-V5 (1/5, 1/4 bias)
3.0
Power VDD V1 V2 V3 V4 V5
Duty Bias
1/8, 1/11 Duty 1/4 Bias VDD VDD - VLCD/4 VDD - VLCD/2 VDD - VLCD/2 VDD - 3VLCD/4 VDD - VLCD
1/16 Duty 1/5 Bias VDD VDD - VLCD/5 VDD - 2VLCD/5 VDD - 3VLCD/5 VDD - 4VLCD/5 VDD - VLCD
32
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
AC Characteristics (VDD = 4.5 to 5.5V, Ta = -30 to +85C) Mode Characteristics E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) Write Mode (refer to Figure-6) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time Read Mode (refer to Figure-7) E Pulse Width (High, Low) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Symbol tc t R, t F tw tsu1 tH1 tsu2 tH2 tc t R, t F tw tsu tH tD tDH Min 500 230 40 10 80 10 500 230 40 10 5 Typ Max 20 20 120 ns ns Unit
(VDD = 2.7 to 4.5V, Ta = -30 to +85C) Mode Characteristic E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) Write Mode (refer to Figure-6) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) Read Mode (refer to Figure-7) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Symbol tc t R, t F tw tsu1 tH1 tsu2 tH2 tc t R, t F tw tsu tH tD tDH Min 1000 450 60 20 195 10 1000 450 60 20 5 Typ Max 25 25 360 ns ns Unit
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S6A0069
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
(VDD = 2.7 to 4.5V, Ta = -30 to +85C) Mode Characteristic Clock Pulse Width (High, Low) Interface Mode with Extension Driver (refer to Figure-8) Clock Rise / Fall Time Clock Setup Time Data Setup Time Data Hold Time M Delay Time Symbol tw t R, t F tsu1 tsu2 tDH tDM Min 800 500 300 300 -1000 Typ Max 25 1000 ns Unit
RS
VIH1 VIL1 tsu1 VIL1 tw
th1 VIL1 th1 tf
R/W
E tr DB0-DB7
VIH1 VIL1 VIH1 VIL1
tsu2 Valid Data tc
th2 VIH1 VIL1
VIL1
Figure 6. Write Mode Timing Diagram
RS
VIH1 VIL1 tsu VIH1 tw
th VIH1 th tf
R/W
E tr DB0-DB7
VIH1 VIL1 tD VOH1 VOL1 tDH VOH1 VOL1
VIL1
Valid Data tc
Figure 7. Read Mode Timing Diagram
34
16COM/40SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0069
tf CLK1 VOH2 tr CLK2 VOH2 VOL2 tSU1 D tSU2 M tDM VOL2 tDH VOH2 tw VOL2 tw VOH2 VOL2 tw VOH2 VOL2
Figure 8. Interface Mode with Extension Driver Timing Diagram
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